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Research infrastructures for hardware accelerators / (Record no. 562172)

000 -LEADER
fixed length control field 05142nam a2200709 i 4500
001 - CONTROL NUMBER
control field 7347037
003 - CONTROL NUMBER IDENTIFIER
control field IEEE
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20200413152919.0
006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS
fixed length control field m eo d
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr cn |||m|||a
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 151124s2016 caua foab 000 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781627058322
Qualifying information ebook
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
Canceled/invalid ISBN 9781627058315
Qualifying information print
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.2200/S00677ED1V01Y201511CAC034
Source of number or code doi
035 ## - SYSTEM CONTROL NUMBER
System control number (CaBNVSL)swl00405829
035 ## - SYSTEM CONTROL NUMBER
System control number (OCoLC)930370858
040 ## - CATALOGING SOURCE
Original cataloging agency CaBNVSL
Language of cataloging eng
Description conventions rda
Transcribing agency CaBNVSL
Modifying agency CaBNVSL
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7895.M5
Item number S427 2016
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3916
Edition number 23
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Shao, Yakun Sophia.,
Relator term author.
245 10 - TITLE STATEMENT
Title Research infrastructures for hardware accelerators /
Statement of responsibility, etc. Yakun Sophia Shao and David Brooks.
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Place of production, publication, distribution, manufacture San Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) :
Name of producer, publisher, distributor, manufacturer Morgan & Claypool,
Date of production, publication, distribution, manufacture, or copyright notice 2016.
300 ## - PHYSICAL DESCRIPTION
Extent 1 PDF (xiii, 85 pages) :
Other physical details illustrations.
336 ## - CONTENT TYPE
Content type term text
Source rdacontent
337 ## - MEDIA TYPE
Media type term electronic
Source isbdmedia
338 ## - CARRIER TYPE
Carrier type term online resource
Source rdacarrier
490 1# - SERIES STATEMENT
Series statement Synthesis lectures on computer architecture,
International Standard Serial Number 1935-3243 ;
Volume/sequential designation # 34
538 ## - SYSTEM DETAILS NOTE
System details note Mode of access: World Wide Web.
538 ## - SYSTEM DETAILS NOTE
System details note System requirements: Adobe Acrobat Reader.
500 ## - GENERAL NOTE
General note Part of: Synthesis digital library of engineering and computer science.
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc. note Includes bibliographical references (pages 73-83).
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note 1. Why accelerators, now? -- 1.1 What is an accelerator? -- 1.2 A tale of two scalings -- 1.2.1 Moore scaling -- 1.2.2 Dennard scaling -- 1.3 The combination of Moore and Dennard scaling -- 1.3.1 Moore + Dennard, where we were -- 1.3.2 Moore scaling only, where we are -- 1.3.3 Dennard only, where we are unlikely to be -- 1.3.4 A future without scaling: "The winter of despair" -- 1.4 To live without scaling: "A spring of hope" -- 1.4.1 Why not architectural scaling? -- 1.4.2 Specialization makes a difference -- 1.4.3 A call for tools in the era of accelerators --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 2. A taxonomy of accelerators -- 2.1 Not all apples are alike -- 2.2 Accelerator taxonomy -- 2.2.1 Accelerators that are part of the pipeline -- 2.2.2 Accelerators that are attached to cache -- 2.2.3 Accelerators that are attached to the memory bus -- 2.2.4 Accelerators that are attached to the I/O bus --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 3. Accelerator design flow 101 -- 3.1 Standard RTL design flow -- 3.2 High-level synthesis -- 3.2.1 Bluespec SystemVerilog -- 3.2.2 Genesis2 -- 3.2.3 Xilinx Vivado -- 3.2.4 Delite -- 3.2.5 Lime -- 3.2.6 ChiseL -- 3.2.7 Spiral -- 3.2.8 PyMTL --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 4. Accelerator modeling -- 4.1 Limitations of the RTL-based design flow -- 4.2 Pre-RTL modeling, Aladdin -- 4.2.1 Optimization phase -- 4.2.2 Realization phase -- 4.2.3 Integration with memory system -- 4.2.4 Limitations -- 4.2.5 Aladdin validation -- 4.2.6 Algorithm-to-solution time -- 4.2.7 Case study: Gemm design space --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 5. Workload characterization for accelerators -- 5.1 ISA-independent workload characterization, WIICA -- 5.1.1 Why ISA-independent? -- 5.1.2 Methodology and background -- 5.1.3 Compute -- 5.1.4 Memory -- 5.1.5 Control -- 5.1.6 Putting it all together --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 6. Accelerator benchmarks --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 7. Future directions -- Bibliography -- Authors' biographies.
506 1# - RESTRICTIONS ON ACCESS NOTE
Terms governing access Abstract freely available; full-text restricted to subscribers or individual document purchasers.
510 0# - CITATION/REFERENCES NOTE
Name of source Compendex
510 0# - CITATION/REFERENCES NOTE
Name of source INSPEC
510 0# - CITATION/REFERENCES NOTE
Name of source Google scholar
510 0# - CITATION/REFERENCES NOTE
Name of source Google book search
520 3# - SUMMARY, ETC.
Summary, etc. Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors, and extensive research infrastructure has been developed to support research efforts in this domain. Envisioning future computing systems with a diverse set of general-purpose cores and accelerators, computer architects must add accelerator-related research infrastructures to their toolboxes to explore future heterogeneous systems. This book serves as a primer for the field, as an overview of the vast literature on accelerator architectures and their design flows, and as a resource guidebook for researchers working in related areas.
530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE
Additional physical form available note Also available in print.
588 ## - SOURCE OF DESCRIPTION NOTE
Source of description note Title from PDF title page (viewed on November 24, 2015).
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Microprocessors
General subdivision Design and construction.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element High performance computing.
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term accelerators
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term specialized architecture
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term SoC
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term high-level synthesis,
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term simulators
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term design space exploration
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term workload characterization
653 ## - INDEX TERM--UNCONTROLLED
Uncontrolled term benchmarks
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Brooks, David.,
Relator term author.
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Relationship information Print version:
International Standard Book Number 9781627058315
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Synthesis digital library of engineering and computer science.
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Synthesis lectures in computer architecture ;
Volume/sequential designation # 34.
International Standard Serial Number 1935-3243
856 42 - ELECTRONIC LOCATION AND ACCESS
Materials specified Abstract with links to resource
Uniform Resource Identifier http://ieeexplore.ieee.org/servlet/opac?bknumber=7347037
Holdings
Withdrawn status Lost status Damaged status Not for loan Permanent Location Current Location Date acquired Barcode Date last seen Price effective from Koha item type
        PK Kelkar Library, IIT Kanpur PK Kelkar Library, IIT Kanpur 2020-04-13 EBKE672 2020-04-13 2020-04-13 E books

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