| 000 -LEADER |
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| fixed length control field |
05957nam a2200721 i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
7154565 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20200413152918.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS |
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| fixed length control field |
m eo d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr cn |||m|||a |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
150725s2015 caua foab 000 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781627057684 |
| Qualifying information |
ebook |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Canceled/invalid ISBN |
9781627057677 |
| Qualifying information |
print |
| 024 7# - OTHER STANDARD IDENTIFIER |
|---|
| Standard number or code |
10.2200/S00650ED1V01Y201505CAC033 |
| Source of number or code |
doi |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(CaBNVSL)swl00405303 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)914432293 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
CaBNVSL |
| Language of cataloging |
eng |
| Description conventions |
rda |
| Transcribing agency |
CaBNVSL |
| Modifying agency |
CaBNVSL |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
QA76.9.A73 |
| Item number |
C443 2015 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
004.22 |
| Edition number |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Chen, Yu-Ting., |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Customizable computing / |
| Statement of responsibility, etc. |
Yu-Ting Chen, Jason Cong, Michael Gill, Glenn Reinman, and Bingjun Xiao. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE |
|---|
| Place of production, publication, distribution, manufacture |
San Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) : |
| Name of producer, publisher, distributor, manufacturer |
Morgan & Claypool, |
| Date of production, publication, distribution, manufacture, or copyright notice |
2015. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
1 PDF (xi, 106 pages) : |
| Other physical details |
illustrations. |
| 336 ## - CONTENT TYPE |
|---|
| Content type term |
text |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
|---|
| Media type term |
electronic |
| Source |
isbdmedia |
| 338 ## - CARRIER TYPE |
|---|
| Carrier type term |
online resource |
| Source |
rdacarrier |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
Synthesis lectures on computer architecture, |
| International Standard Serial Number |
1935-3243 ; |
| Volume/sequential designation |
# 33 |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
Mode of access: World Wide Web. |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
System requirements: Adobe Acrobat Reader. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Part of: Synthesis digital library of engineering and computer science. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references (pages 89-103). |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
1. Introduction -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
2. Road map -- 2.1 Customizable system-on-chip design -- 2.1.1 Compute resources -- 2.1.2 On-chip memory hierarchy -- 2.1.3 Network-on-chip -- 2.2 Software layer -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
3. Customization of cores -- 3.1 Introduction -- 3.2 Dynamic core scaling and defeaturing -- 3.3 Core fusion -- 3.4 Customized instruction set extensions -- 3.4.1 Vector instructions -- 3.4.2 Custom compute engines -- 3.4.3 Reconfigurable instruction sets -- 3.4.4 Compiler support for custom instructions -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
4. Loosely coupled compute engines -- 4.1 Introduction -- 4.2 Loosely coupled accelerators -- 4.2.1 Wire-speed processor -- 4.2.2 Comparing hardware and software LCA management -- 4.2.3 Utilizing LCAs -- 4.3 Accelerators using field programmable gate arrays -- 4.4 Coarse-grain reconfigurable arrays -- 4.4.1 Static mapping -- 4.4.2 Run-time mapping -- 4.4.3 CHARM -- 4.4.4 Using composable accelerators -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
5. On-chip memory customization -- 5.1 Introduction -- 5.1.1 Caches and buffers (scratchpads) -- 5.1.2 On-chip memory system customizations -- 5.2 CPU cache customizations -- 5.2.1 Coarse-grain customization strategies -- 5.2.2 Fine-grain customization strategies -- 5.3 Buffers for accelerator-rich architectures -- 5.3.1 Shared buffer system design for accelerators -- 5.3.2 Customization of buffers inside an accelerator -- 5.4 Providing buffers in caches for CPUs and accelerators -- 5.4.1 Providing software-managed scratchpads for CPUs -- 5.4.2 Providing buffers for accelerators -- 5.5 Caches with disparate memory technologies -- 5.5.1 Coarse-grain customization strategies -- 5.5.2 Fine-grain customization strategies -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
6. Interconnect customization -- 6.1 Introduction -- 6.2 Topology customization -- 6.2.1 Application-specific topology synthesis -- 6.2.2 Reconfigurable shortcut insertion -- 6.2.3 Partial crossbar synthesis and reconfiguration -- 6.3 Routing customization -- 6.3.1 Application-aware deadlock-free routing -- 6.3.2 Data flow synthesis -- 6.4 Customization enabled by new device/circuit technologies -- 6.4.1 Optical interconnects -- 6.4.2 Radio-frequency interconnects -- 6.4.3 RRAM-based interconnects -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
7. Concluding remarks -- Bibliography -- Authors' biographies. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE |
|---|
| Terms governing access |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Compendex |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
INSPEC |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google scholar |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google book search |
| 520 3# - SUMMARY, ETC. |
|---|
| Summary, etc. |
Since the end of Dennard scaling in the early 2000s, improving the energy efficiency of computation has been the main concern of the research community and industry. The large energy efficiency gap between general-purpose processors and application-specific integrated circuits (ASICs) motivates the exploration of customizable architectures, where one can adapt the architecture to the workload. In this Synthesis lecture, we present an overview and introduction of the recent developments on energy-efficient customizable architectures, including customizable cores and accelerators, on-chip memory customization, and interconnect optimization. In addition to a discussion of the general techniques and classification of different approaches used in each area, we also highlight and illustrate some of the most successful design examples in each category and discuss their impact on performance and energy efficiency. We hope that this work captures the state-of-the-art research and development on customizable architectures and serves as a useful reference basis for further research, design, and implementation for large-scale deployment in future computing systems. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE |
|---|
| Additional physical form available note |
Also available in print. |
| 588 ## - SOURCE OF DESCRIPTION NOTE |
|---|
| Source of description note |
Title from PDF title page (viewed on July 25, 2015). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Computer architecture. |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
accelerator architectures |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
memory architecture |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
multiprocessor interconnection |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
parallel architectures |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
reconfigurable architectures |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
memory |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
green computing |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Cong, Jason., |
| Relator term |
author. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Gill, Michael., |
| Relator term |
author. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Reinman, Glenn., |
| Relator term |
author. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Xiao, Bingjun., |
| Relator term |
author. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Relationship information |
Print version: |
| International Standard Book Number |
9781627057677 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis digital library of engineering and computer science. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis lectures in computer architecture ; |
| Volume/sequential designation |
# 33. |
| International Standard Serial Number |
1935-3243 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Abstract with links to resource |
| Uniform Resource Identifier |
http://ieeexplore.ieee.org/servlet/opac?bknumber=7154565 |
