| 000 -LEADER |
|---|
| fixed length control field |
05472nam a2200661 i 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
7036193 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20200413152916.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS |
|---|
| fixed length control field |
m eo d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
|---|
| fixed length control field |
cr cn |||m|||a |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
150117s2015 caua foab 000 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781627056465 |
| Qualifying information |
ebook |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Canceled/invalid ISBN |
9781627056458 |
| Qualifying information |
print |
| 024 7# - OTHER STANDARD IDENTIFIER |
|---|
| Standard number or code |
10.2200/S00611ED1V01Y201411CAC030 |
| Source of number or code |
doi |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(CaBNVSL)swl00404601 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)900340877 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
CaBNVSL |
| Language of cataloging |
eng |
| Description conventions |
rda |
| Transcribing agency |
CaBNVSL |
| Modifying agency |
CaBNVSL |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
QA76.9.A73 |
| Item number |
S526 2015 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
004.22 |
| Edition number |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Själander, Magnus, |
| Dates associated with a name |
1977-, |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Power-efficient computer architectures : |
| Remainder of title |
recent advances / |
| Statement of responsibility, etc. |
Magnus Själander, Margaret Martonosi, Stefanos Kaxiras. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE |
|---|
| Place of production, publication, distribution, manufacture |
San Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) : |
| Name of producer, publisher, distributor, manufacturer |
Morgan & Claypool, |
| Date of production, publication, distribution, manufacture, or copyright notice |
2015. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
1 PDF (xi, 84 pages) : |
| Other physical details |
illustrations. |
| 336 ## - CONTENT TYPE |
|---|
| Content type term |
text |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
|---|
| Media type term |
electronic |
| Source |
isbdmedia |
| 338 ## - CARRIER TYPE |
|---|
| Carrier type term |
online resource |
| Source |
rdacarrier |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
Synthesis lectures on computer architecture, |
| International Standard Serial Number |
1935-3243 ; |
| Volume/sequential designation |
# 30 |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
Mode of access: World Wide Web. |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
System requirements: Adobe Acrobat Reader. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Part of: Synthesis digital library of engineering and computer science. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references (pages 61-81). |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
1. Introduction -- 1.1 From the beginning -- 1.2 The end of Dennard scaling and the switch to multicores -- 1.3 Dark silicon, the utilization wall, and the rise of the heterogeneous parallelism -- 1.4 Other issues and future directions -- 1.5 About the book -- 1.5.1 Differences from the prior synthesis lecture [103] -- 1.5.2 Target audience -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
2. Voltage and frequency management -- 2.1 Technology background and trends -- 2.1.1 Relation of V and f -- 2.1.2 Technology solutions -- 2.1.3 DVFS latency -- 2.1.4 DVFS granularity -- 2.2 Models of frequency vs. performance and power -- 2.2.1 Analytical models -- 2.2.2 Correlation-based power models -- 2.2.3 A combined power and performance model -- 2.3 OS-managed DVFS techniques -- 2.3.1 Discovering and exploiting deadlines -- 2.3.2 Linux DVFS governors -- 2.4 Parallelism and criticality -- 2.4.1 Thread- and task-level criticality: static scheduling -- 2.4.2 Thread- and task-level criticality: dynamic scheduling -- 2.4.3 Criticality -- 2.5 Chapter summary -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
3. Heterogeneity and specialization -- 3.1 Dark silicon -- 3.1.1 Dark silicon analysis and models -- 3.1.2 Designing for dark silicon: brief examples -- 3.1.3 The sentiments against dark silicon -- 3.2 Heterogeneity in on-chip CPUs -- 3.2.1 Current industry approaches -- 3.2.2 Research and future trends -- 3.3 Single-ISA configurable heterogeneity -- 3.4 Mixing GPUs and CPUs -- 3.4.1 CPU-GPU pairs: the power-performance rationale -- 3.4.2 Industry examples -- 3.4.3 Selected research examples -- 3.5 Accelerators -- 3.5.1 Background -- 3.5.2 Selected research -- 3.5.3 Industry examples -- 3.6 Reliability vs. energy tradeoffs -- 3.7 Chapter summary -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
4. Communication and memory systems -- 4.1 The energy cost of data motion: a holistic view -- 4.2 Power awareness in on-chip interconnect: techniques and trends -- 4.2.1 Background and industry state -- 4.2.2 Power efficiency of interconnect links -- 4.2.3 Exploiting emerging technologies to improve power efficiency -- 4.3 Power awareness in data storage: caches and scratchpads -- 4.3.1 Cache hierarchies and power efficiency -- 4.3.2 Cache associativity and its implication on power -- 4.3.3 Cache resizing and static power -- 4.3.4 Cache coherence -- 4.3.5 The power implications of scratchpad memories -- 4.4 Chapter summary -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
5. Conclusions -- 5.1 Future trends: technology challenges and drivers -- 5.2 Future trends: emerging applications and domains -- 5.3 Final summary -- Bibliography -- Authors' biographies. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE |
|---|
| Terms governing access |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Compendex |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
INSPEC |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google scholar |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google book search |
| 520 3# - SUMMARY, ETC. |
|---|
| Summary, etc. |
As Moore's Law and Dennard scaling trends have slowed, the challenges of building high-performance computer architectures while maintaining acceptable power efficiency levels have heightened. Over the past ten years, architecture techniques for power efficiency have shifted from primarily focusing on module-level efficiencies, toward more holistic design styles based on parallelism and heterogeneity. This work highlights and synthesizes recent techniques and trends in power-efficient computer architecture. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE |
|---|
| Additional physical form available note |
Also available in print. |
| 588 ## - SOURCE OF DESCRIPTION NOTE |
|---|
| Source of description note |
Title from PDF title page (viewed on January 17, 2015). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Computer architecture. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electronic digital computers |
| General subdivision |
Power supply. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electric power |
| General subdivision |
Conservation. |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
power |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
architecture |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
parallelism |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
heterogeneity |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Martonosi, Margaret., |
| Relator term |
author. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Kaxiras, Stefanos., |
| Relator term |
author. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Relationship information |
Print version: |
| International Standard Book Number |
9781627056458 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis digital library of engineering and computer science. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis lectures in computer architecture ; |
| Volume/sequential designation |
# 30. |
| International Standard Serial Number |
1935-3243 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Abstract with links to resource |
| Uniform Resource Identifier |
http://ieeexplore.ieee.org/servlet/opac?bknumber=7036193 |
