| 000 -LEADER |
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| fixed length control field |
07878nam a2200709 i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
6812620 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20200413152910.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS |
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m eo d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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cr cn |||m|||a |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
130718s2013 caua foab 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9781627050616 (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Canceled/invalid ISBN |
9781627050609 (pbk.) |
| 024 7# - OTHER STANDARD IDENTIFIER |
|---|
| Standard number or code |
10.2200/S00514ED1V01Y201306DTM035 |
| Source of number or code |
doi |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(CaBNVSL)swl00402610 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)853273076 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
CaBNVSL |
| Transcribing agency |
CaBNVSL |
| Modifying agency |
CaBNVSL |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7895.G36 |
| Item number |
T483 2013 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.395 |
| Edition number |
23 |
| 090 ## - LOCALLY ASSIGNED LC-TYPE CALL NUMBER (OCLC); LOCAL CALL NUMBER (RLIN) |
|---|
| Classification number (OCLC) (R) ; Classification number, CALL (RLIN) (NR) |
|
| Local cutter number (OCLC) ; Book number/undivided call number, CALL (RLIN) |
MoCl |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Teubner, Jens. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Data processing on FPGAs |
| Medium |
[electronic resource] / |
| Statement of responsibility, etc. |
Jens Teubner, Louis Woods. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : |
| Name of publisher, distributor, etc. |
Morgan & Claypool, |
| Date of publication, distribution, etc. |
c2013. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
1 electronic text (xiv, 104 p.) : |
| Other physical details |
ill., digital file. |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
Synthesis lectures on data management, |
| International Standard Serial Number |
2153-5426 ; |
| Volume/sequential designation |
# 35 |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
Mode of access: World Wide Web. |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
System requirements: Adobe Acrobat Reader. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Part of: Synthesis digital library of engineering and computer science. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Series from website. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references (p. 95-100) and index. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
1. Introduction -- 1.1 Moore's law and transistor-speed scaling -- 1.2 Memory wall and Von Neumann bottleneck -- 1.3 Power wall -- 1.4 Multicore CPUs and GPUs -- 1.5 Specialized hardware -- 1.6 Field-programmable gate arrays (FPGAs) -- 1.7 FPGAs for data processing -- 1.7.1 Stream processing -- 1.7.2 Big data -- 1.7.3 Cloud computing -- 1.7.4 Security -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
2. A primer in hardware design -- 2.1 Basic hardware components -- 2.1.1 Combinational logic -- 2.1.2 Sequential logic -- 2.1.3 Asynchronous sequential logic -- 2.1.4 Synchronous sequential logic -- 2.2 Hardware programming -- 2.2.1 Hardware description languages (HDLs) -- 2.3 Circuit generation -- 2.3.1 Logical design flow (Synthesis) -- 2.3.2 Physical design flow -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
3. FPGAs -- 3.1 A brief history of FPGAs -- 3.2 Look-up tables, the key to re-programmability -- 3.2.1 LUT representation of a Boolean function -- 3.2.2 Internal architecture of an LUT -- 3.2.3 LUT (Re)programming -- 3.2.4 Alternative usage of LUTs -- 3.3 FPGA architecture -- 3.3.1 Elementary logic units (Slices/ALMs) -- 3.4 Routing architecture -- 3.4.1 Logic islands -- 3.4.2 Interconnect -- 3.5 High-speed I/O -- 3.6 Auxiliary on-chip components -- 3.6.1 Block RAM (BRAM) -- 3.6.2 Digital signal processing (DSP) units -- 3.6.3 Soft and hard IP-cores -- 3.7 FPGA programming -- 3.7.1 FPGA design flow -- 3.7.2 Dynamic partial reconfiguration -- 3.8 Advanced technology and future trends -- 3.8.1 Die stacking -- 3.8.2 Heterogeneous die-stacked FPGAs -- 3.8.3 Time-multiplexed FPGAs -- 3.8.4 High-level synthesis -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
4. FPGA programming models -- 4.1 Re-build, parameterize, or program the hardware accelerator? -- 4.1.1 Re-building circuits at runtime -- 4.1.2 Parameterized circuits -- 4.1.3 Instruction set processors on top of FPGAs -- 4.2 From algorithm to circuit -- 4.2.1 Expression [to] circuit -- 4.2.2 Circuit generation -- 4.2.3 High-level synthesis -- 4.3 Data-parallel approaches -- 4.3.1 Data parallelism -- 4.4 Pipeline-parallel approaches -- 4.4.1 Pipeline parallelism in hardware -- 4.4.2 Pipelining in FPGAs -- 4.4.3 Designing for pipeline parallelism -- 4.4.4 Turning a circuit into a pipeline-parallel circuit -- 4.5 Related concepts -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
5. Data stream processing -- 5.1 Regular expression matching -- 5.1.1 Finite-state automata for pattern matching -- 5.1.2 Implementing finite-state automata in hardware -- 5.1.3 Optimized circuit construction -- 5.1.4 Network intrusion detection -- 5.2 Complex event processing -- 5.2.1 Stream partitioning -- 5.2.2 Hardware partitioner -- 5.2.3 Best-effort allocation -- 5.2.4 Line-rate performance -- 5.3 Filtering in the data path -- 5.3.1 Data path architecture in the real world -- 5.4 Data stream processing -- 5.4.1 Compositional query compilation -- 5.4.2 Getting data in and out -- 5.5 Dynamic query workloads -- 5.5.1 Fast workload changes through partial modules -- 5.6 Bibliographic notes -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
6. Accelerated DB operators -- 6.1 Sort operator -- 6.1.1 Sorting networks -- 6.1.2 BRAM-based FIFO merge sorter -- 6.1.3 External sorting with a tree merge sorter -- 6.1.4 Sorting with partial reconfiguration -- 6.2 Skyline operator -- 6.2.1 Standard block nested loops (BNL) algorithm -- 6.2.2 Parallel BNL with FPGAs -- 6.2.3 Performance characteristics -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
7. Secure data processing -- 7.1 FPGAs versus CPUs -- 7.1.1 Von Neumann architecture -- 7.1.2 Trusted platform module (TPM) -- 7.2 FPGAs versus ASICs -- 7.3 Security properties of FPGAs -- 7.3.1 Bitstream encryption -- 7.3.2 Bitstream authentication -- 7.3.3 Further security mechanisms -- 7.4 FPGA as trusted hardware -- 7.4.1 Fully homomorphic encryption with FPGAs -- 7.4.2 Hybrid data processing -- 7.4.3 Trusted hardware implementation -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
8. Conclusions -- A. Commercial FPGA cards -- A1. NetFPGA -- A2. Solarflare's applicationOnload engine -- A3.Fusion I/O's ioDrive -- Bibliography -- Authors' biographies -- Index. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE |
|---|
| Terms governing access |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Compendex |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
INSPEC |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google scholar |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google book search |
| 520 3# - SUMMARY, ETC. |
|---|
| Summary, etc. |
Roughly a decade ago, power consumption and heat dissipation concerns forced the semiconductor industry to radically change its course, shifting from sequential to parallel computing. Unfortunately, improving performance of applications has now become much more difficult than in the good old days of frequency scaling. This is also affecting databases and data processing applications in general, and has led to the popularity of so-called data appliances, specialized data processing engines, where software and hardware are sold together in a closed box. Field-programmable gate arrays (FPGAs) increasingly play an important role in such systems. FPGAs are attractive because the performance gains of specialized hardware can be significant, while power consumption is much less than that of commodity processors. On the other hand, FPGAs are way more flexible than hard-wired circuits (ASICs) and can be integrated into complex systems in many different ways, e.g., directly in the network for a high-frequency trading application. This book gives an introduction to FPGA technology targeted at a database audience. In the first few chapters, we explain in detail the inner workings of FPGAs. ?en we discuss techniques and design patterns that help mapping algorithms to FPGA hardware so that the inherent parallelism of these devices can be leveraged in an optimal way. Finally, the book will illustrate a number of concrete examples that exploit different advantages of FPGAs for data processing. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE |
|---|
| Additional physical form available note |
Also available in print. |
| 588 ## - SOURCE OF DESCRIPTION NOTE |
|---|
| Source of description note |
Title from PDF t.p. (viewed on July 18, 2013). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Field programmable gate arrays. |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
FPGA |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
modern hardware |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
database |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
data processing |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
stream processing |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
parallel algorithms |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
pipeline parallelism |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
programming models |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Woods, Louis. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Relationship information |
Print version: |
| International Standard Book Number |
9781627050609 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis digital library of engineering and computer science. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis lectures on data management ; |
| Volume/sequential designation |
# 35. |
| International Standard Serial Number |
2153-5426 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Abstract with links to resource |
| Uniform Resource Identifier |
http://ieeexplore.ieee.org/servlet/opac?bknumber=6812620 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Abstract with links to full text |
| Uniform Resource Identifier |
http://dx.doi.org/10.2200/S00514ED1V01Y201306DTM035 |
