| 000 -LEADER |
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| fixed length control field |
05842nam a2200637 i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
6812580 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20200413152909.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS |
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m eo d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr cn |||m|||a |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
130217s2013 caua foab 000 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781608458561 (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Canceled/invalid ISBN |
9781608458554 (pbk.) |
| 024 7# - OTHER STANDARD IDENTIFIER |
|---|
| Standard number or code |
10.2200/S00458ED1V01Y201212CAC021 |
| Source of number or code |
doi |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(CaBNVSL)swl00402158 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)827936289 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
CaBNVSL |
| Transcribing agency |
CaBNVSL |
| Modifying agency |
CaBNVSL |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
QA76.9.A73 |
| Item number |
N455 2013 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
004.22 |
| Edition number |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Nemirovsky, Mario. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Multithreading architecture |
| Medium |
[electronic resource] / |
| Statement of responsibility, etc. |
Mario Nemirovsky, Dean M. Tullsen. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : |
| Name of publisher, distributor, etc. |
Morgan & Claypool, |
| Date of publication, distribution, etc. |
c2013. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
1 electronic text (xiv, 95 p.) : |
| Other physical details |
ill., digital file. |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
Synthesis lectures on computer architecture, |
| International Standard Serial Number |
1935-3243 ; |
| Volume/sequential designation |
# 21 |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
Mode of access: World Wide Web. |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
System requirements: Adobe Acrobat Reader. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Part of: Synthesis digital library of engineering and computer science. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Series from website. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references (p. 83-94). |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Preface -- 1. Introduction -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
2. Multithreaded execution models -- 2.1 Chip multiprocessors -- 2.2 Conjoined core architectures -- 2.3 Coarse-grain multithreading -- 2.4 Fine-grain multithreading -- 2.5 Simultaneous multithreading -- 2.6 Hybrid models -- 2.7 GPUs and warp scheduling -- 2.8 Summary -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
3. Coarse-grain multithreading -- 3.1 Historical context -- 3.2 A reference implementation of CGMT -- 3.2.1 Changes to IF -- 3.2.2 Changes to RD -- 3.2.3 Changes to ALU -- 3.2.4 Changes to MEM -- 3.2.5 Changes to WB -- 3.2.6 Swapping contexts -- 3.2.7 Superscalar considerations -- 3.3 Coarse-grain multithreading for modern architectures -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
4. Fine-grain multithreading -- 4.1 Historical context -- 4.2 A reference implementation of FGMT -- 4.2.1 Changes to IF -- 4.2.2 Changes to RD -- 4.2.3 Changes to ALU -- 4.2.4 Changes to MEM -- 4.2.5 Changes to WB -- 4.2.6 Superscalar considerations -- 4.3 Fine-grain multithreading for modern architectures -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
5. Simultaneous multithreading -- 5.1 Historical context -- 5.2 A reference implementation of SMT -- 5.2.1 Changes to fetch -- 5.2.2 Changes to DEC/MAP -- 5.2.3 Changes to Issue/RF -- 5.2.4 Other pipeline stages -- 5.3 Superscalar vs. VLIW; in-order vs. out-of-order -- 5.4 Simultaneous multithreading for modern architectures -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
6. Managing contention -- 6.1 Managing cache and memory contention -- 6.2 Branch predictor contention -- 6.3 Managing contention through the fetch unit -- 6.4 Managing register files -- 6.5 Operating system thread scheduling -- 6.6 Compiling for multithreaded processors -- 6.7 Multithreaded processor synchronization -- 6.8 Security on multithreaded systems -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
7. New opportunities for multithreaded processors -- 7.1 Helper threads and non-traditional parallelism -- 7.2 Fault tolerance -- 7.3 Speculative multithreading on multithreaded processors -- 7.4 Energy and power -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
8. Experimentation and metrics -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
9. Implementations of multithreaded processors -- 9.1 Early machines, DYSEAC and the Lincoln TX-2 -- 9.2 CDC 6600 -- 9.3 Denelcor HEP -- 9.4 Horizon -- 9.5 Delco TIO -- 9.6 Tera MTA -- 9.7 MIT Sparcle -- 9.8 DEC/Compaq Alpha 21464 -- 9.9 Clearwater Networks CNP810SP -- 9.10 ConSentry Networks LSP-1 -- 9.11 Pentium 4 -- 9.12 Sun Ultrasparc (Niagara) T1 and T2 -- 9.13 Sun MAJC and ROCK -- 9.14 IBM Power -- 9.15 AMD Bulldozer -- 9.16 Intel Nehalem -- 9.17 Summary -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Bibliography -- Authors' biographies. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE |
|---|
| Terms governing access |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Compendex |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
INSPEC |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google scholar |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google book search |
| 520 3# - SUMMARY, ETC. |
|---|
| Summary, etc. |
Multithreaded architectures now appear across the entire range of computing devices, from the highest-performing general purpose devices to low-end embedded processors. Multithreading enables a processor core to more effectively utilize its computational resources, as a stall in one thread need not cause execution resources to be idle. This enables the computer architect to maximize performance within area constraints, power constraints, or energy constraints. However, the architectural options for the processor designer or architect looking to implement multithreading are quite extensive and varied, as evidenced not only by the research literature but also by the variety of commercial implementations. This book introduces the basic concepts of multithreading, describes the a number of models of multithreading, and then develops the three classic models (coarse-grain, fine-grain, and simultaneous multithreading) in greater detail. It describes a wide variety of architectural and software design tradeoffs, as well as opportunities specific to multithreading architectures. Finally, it details a number of important commercial and academic hardware implementations of multithreading. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE |
|---|
| Additional physical form available note |
Also available in print. |
| 588 ## - SOURCE OF DESCRIPTION NOTE |
|---|
| Source of description note |
Title from PDF t.p. (viewed on February 17, 2013). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Simultaneous multithreading processors. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Computer architecture. |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
multithreading |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Tullsen, Dean M. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Relationship information |
Print version: |
| International Standard Book Number |
9781608458554 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis digital library of engineering and computer science. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis lectures in computer architecture ; |
| Volume/sequential designation |
# 21. |
| International Standard Serial Number |
1935-3243 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Abstract with links to resource |
| Uniform Resource Identifier |
http://ieeexplore.ieee.org/servlet/opac?bknumber=6812580 |
