| 000 -LEADER |
|---|
| fixed length control field |
07598nam a2200745 i 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
6812976 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20200413152908.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS |
|---|
| fixed length control field |
m eo d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
|---|
| fixed length control field |
cr cn |||m|||a |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
130217s2013 caua foab 000 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781627050234 (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| Canceled/invalid ISBN |
9781627050227 (pbk.) |
| 024 7# - OTHER STANDARD IDENTIFIER |
|---|
| Standard number or code |
10.2200/S00472ED1V01Y201301DCS040 |
| Source of number or code |
doi |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(CaBNVSL)swl00402156 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)827937191 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
CaBNVSL |
| Transcribing agency |
CaBNVSL |
| Modifying agency |
CaBNVSL |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
QC176.8.N35 |
| Item number |
I585 2013 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
537.6226 |
| Edition number |
23 |
| 245 00 - TITLE STATEMENT |
|---|
| Title |
Introduction to noise-resilient computing |
| Medium |
[electronic resource] / |
| Statement of responsibility, etc. |
S.N. Yanushkevich ... [et al.]. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : |
| Name of publisher, distributor, etc. |
Morgan & Claypool, |
| Date of publication, distribution, etc. |
c2013. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
1 electronic text (xix, 132 p.) : |
| Other physical details |
ill., digital file. |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
Synthesis lectures on digital circuits and systems, |
| International Standard Serial Number |
1932-3174 ; |
| Volume/sequential designation |
# 40 |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
Mode of access: World Wide Web. |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
System requirements: Adobe Acrobat Reader. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Part of: Synthesis digital library of engineering and computer science. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Series from website. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references (p. 117-129). |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Preface -- Acknowledgments -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
1. Introduction to probabilistic computation models -- 1.1 Why do we need probabilistic models? -- 1.1.1 Noise -- 1.1.2 Ideal noise-free conditions -- 1.1.3 Noisy operation conditions -- 1.2 Probabilistic techniques and models -- 1.2.1 Popular probabilistic techniques -- 1.2.2 Probabilistic models based on local computation -- 1.2.3 Nearest neighbor methodologies -- 1.2.4 Bayesian belief propagation model -- 1.2.5 Markov random field model -- 1.2.6 Neuromorphic model -- 1.3 Hardware implementation -- 1.4 Concluding remarks -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
2. Nanoscale circuits and fluctuation problems -- 2.1 Nanostructures for logic circuits -- 2.1.1 Why nanostructures? -- 2.1.2 Nanostructure formation -- 2.1.3 Nanostructure network and switching function for circuitry -- 2.2 Fluctuation in nanodevices and their integrated circuits -- 2.3 Concluding remarks -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
3. Estimators and metrics -- 3.1 Why do we need new metrics? -- 3.1.1 Objective and subjective measures of belief -- 3.1.2 Logic operations and data structures -- 3.1.3 Operations with probabilities and data structure -- 3.1.4 Measures of uncertainty -- 3.2 Uncertainty representation and estimation -- 3.2.1 Variability and random variables -- 3.2.2 Parameter estimation -- 3.2.3 Probability metrics -- 3.2.4 Information-theoretic metrics -- 3.3 Measurement techniques -- 3.3.1 Kullback-Leibler divergence -- 3.3.2 Signal-to-noise ratio (SNR) -- 3.3.3 Bit error rate (BER) -- 3.4 Maximum-likelihood estimators -- 3.4.1 Formal notation -- 3.4.2 The simplest estimator -- 3.4.3 The best hardware estimator -- 3.5 Summary and discussion -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
4. MRF models of logic gates -- 4.1 Basic definitions -- 4.1.1 Graphical data structure -- 4.1.2 Formal notion of the MRF model -- 4.1.3 Logic function embedding -- 4.1.4 Implementation -- 4.2 MRF model of a binary inverter -- 4.2.1 Marginalization -- 4.2.2 Compatibility truth table -- 4.2.3 Feedback -- 4.3 MRF model implementation using cyclic BDDs -- 4.3.1 Measures for BDTs and BDDs -- 4.3.2 Cyclic BDTs and BDDs -- 4.4 Simulation -- 4.4.1 NOT gate CMOS implementation using a cyclic BDD -- 4.4.2 Comparison -- 4.5 Noise-tolerant two-bit adder -- 4.5.1 Shared BDDs -- 4.5.2 Shared cyclic BDD -- 4.6 Experimental study -- 4.6.1 Comparisons of two-bit adders -- 4.6.2 Area, power, and delay -- 4.6.3 Simulation results -- 4.7 Ternary inverter -- 4.7.1 Noise-tolerant ternary inverter -- 4.7.2 Ternary CMOS NOT and MIN-NOT gate -- 4.7.3 Comparison with conventional CMOS design -- 4.7.4 Area, power, and delay -- 4.8 Summary and discussion -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
5. Neuromorphic models -- 5.1 Hopfield network and Boltzmann machine -- 5.1.1 Threshold gate -- 5.1.2 Noise and measure of uncertainty -- 5.1.3 Network of threshold cells -- 5.1.4 Hopfield network -- 5.1.5 Boltzmann machine -- 5.1.6 Logic function embedding -- 5.2 Experiments -- 5.2.1 Metric -- 5.2.2 Updating -- 5.2.3 Networking Hopfield models of gates -- 5.2.4 Modeling and results -- 5.3 Multistate Hopfield model -- 5.4 Concluding remarks -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
6. Noise-tolerance via error correcting -- 6.1 Introduction -- 6.2 Background of error correcting techniques -- 6.3 Logic gate reliability -- 6.3.1 Multiplexer circuit reliabilitY -- 6.4 Noise modeling in BDDS -- 6.5 BDD model with error correction -- 6.5.1 BDDs for shortened codes -- 6.6 Reliability of error-correcting BDDs -- 6.7 Summary and discussion -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
7. Conclusion and future work -- Bibliography -- Authors' biographies. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE |
|---|
| Terms governing access |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Compendex |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
INSPEC |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google scholar |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google book search |
| 520 3# - SUMMARY, ETC. |
|---|
| Summary, etc. |
Noise abatement is the key problem of small-scaled circuit design. New computational paradigms are needed; as these circuits shrink, they become very vulnerable to noise and soft errors. In this lecture, we present a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation. Among many probabilistic techniques for modeling such devices, only a few models satisfy the requirements of efficient hardware implementation; specifically, Boltzman machines and Markov Random Field (MRF) models. These models have similar built-in noise-immunity characteristics based on feedback mechanisms. In probabilistic models, the values 0 and 1 of logic functions are replaced by degrees of beliefs that these values occur. An appropriate metric for degree of belief is probability. We discuss various approaches for noise-resilient logic gate design, and propose a novel design taxonomy based on implementation of the MRF model by a new type of binary decision diagram (BDD), called a cyclic BDD. In this approach, logic gates and circuits are designed using 2-to-1 bi-directional switches. Such circuits are often modeled using Shannon expansions with the corresponding graph based implementation, BDDs. Simulation experiments are reported to show the noise immunity of the proposed structures. Audiences who may benefit from this lecture include graduate students taking classes on advanced computing device design, and academic and industrial researchers. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE |
|---|
| Additional physical form available note |
Also available in print. |
| 588 ## - SOURCE OF DESCRIPTION NOTE |
|---|
| Source of description note |
Title from PDF t.p. (viewed on February 17, 2013). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Nanoelectromechanical systems |
| General subdivision |
Noise. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Fault-tolerant computing. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Integrated circuits |
| General subdivision |
Fault tolerance. |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
nanotechnology |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
nanostructure |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
nanodevice |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
fluctuation |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
logic gate |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
noise-tolerance |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
fault-tolerance |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Bayesian network |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Markov random field |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Hopfield model |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Boltzmann machine |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
binary decision diagram |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Yanushkevich, Svetlana N. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Relationship information |
Print version: |
| International Standard Book Number |
9781627050227 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis digital library of engineering and computer science. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis lectures on digital circuits and systems ; |
| Volume/sequential designation |
# 40. |
| International Standard Serial Number |
1932-3174 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Abstract with links to resource |
| Uniform Resource Identifier |
http://ieeexplore.ieee.org/servlet/opac?bknumber=6812976 |
