000 -LEADER |
fixed length control field |
06772nam a2200673 i 4500 |
001 - CONTROL NUMBER |
control field |
6813358 |
003 - CONTROL NUMBER IDENTIFIER |
control field |
IEEE |
005 - DATE AND TIME OF LATEST TRANSACTION |
control field |
20200413152904.0 |
006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS |
fixed length control field |
m eo d |
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
fixed length control field |
cr cn |||m|||a |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
111217s2012 caua foab 000 0 eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9781608456666 (electronic bk.) |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
Canceled/invalid ISBN |
9781608456659 (pbk.) |
024 7# - OTHER STANDARD IDENTIFIER |
Standard number or code |
10.2200/S00381ED1V01Y201109CAC018 |
Source of number or code |
doi |
035 ## - SYSTEM CONTROL NUMBER |
System control number |
(CaBNVSL)swl00400318 |
035 ## - SYSTEM CONTROL NUMBER |
System control number |
(OCoLC)767747932 |
040 ## - CATALOGING SOURCE |
Original cataloging agency |
CaBNVSL |
Transcribing agency |
CaBNVSL |
Modifying agency |
CaBNVSL |
050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
Classification number |
TK7895.M4 |
Item number |
Q746 2012 |
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
004.5 |
Edition number |
22 |
100 1# - MAIN ENTRY--PERSONAL NAME |
Personal name |
Qureshi, Moinuddin Khalil Ahmed, |
Dates associated with a name |
1978- |
245 10 - TITLE STATEMENT |
Title |
Phase change memory |
Medium |
[electronic resource] : |
Remainder of title |
from devices to systems / |
Statement of responsibility, etc. |
Moinuddin K. Qureshi, Sudhanva Gurumurthi, Bipin Rajendran. |
260 ## - PUBLICATION, DISTRIBUTION, ETC. |
Place of publication, distribution, etc. |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : |
Name of publisher, distributor, etc. |
Morgan & Claypool, |
Date of publication, distribution, etc. |
c2012. |
300 ## - PHYSICAL DESCRIPTION |
Extent |
1 electronic text (xiii, 120 p.) : |
Other physical details |
ill., digital file. |
490 1# - SERIES STATEMENT |
Series statement |
Synthesis lectures on computer architecture, |
International Standard Serial Number |
1935-3243 ; |
Volume/sequential designation |
# 18 |
538 ## - SYSTEM DETAILS NOTE |
System details note |
Mode of access: World Wide Web. |
538 ## - SYSTEM DETAILS NOTE |
System details note |
System requirements: Adobe Acrobat Reader. |
500 ## - GENERAL NOTE |
General note |
Part of: Synthesis digital library of engineering and computer science. |
500 ## - GENERAL NOTE |
General note |
Series from website. |
504 ## - BIBLIOGRAPHY, ETC. NOTE |
Bibliography, etc. note |
Includes bibliographical references (p. 95-118). |
505 0# - FORMATTED CONTENTS NOTE |
Formatted contents note |
1. Next generation memory technologies -- 1.1 Introduction -- 1.2 Next generation memory technologies, a desiderata -- 1.3 Overview of flash memory and other leading contenders -- 1.3.1 Flash memory -- 1.3.2 Ferro-electric RAM -- 1.3.3 Magnetic & spin-torque transfer RAM -- 1.3.4 Resistive RAM -- 1.3.5 Emerging memory candidates at a glance -- 1.4 Phase change memory -- 1.4.1 PCM materials/device physics -- 1.4.2 Physics of PCM programming and scaling theory -- 1.4.3 Memory cell and array design -- 1.4.4 MLC programming in PCM -- 1.4.5 Reliability -- 1.4.6 PCM technology maturity -- 1.4.7 Concluding remarks -- |
505 8# - FORMATTED CONTENTS NOTE |
Formatted contents note |
2. Architecting PCM for main memories -- 2.1 Introduction -- 2.2 PCM benefits and challenges -- 2.3 PCM tailored array organization -- 2.4 Fine-grained write filtering -- 2.5 Hybrid memory: combining DRAM and PCM -- 2.5.1 Optimizations for hybrid memory -- 2.5.2 Performance of hybrid memory -- 2.6 Concluding -- |
505 8# - FORMATTED CONTENTS NOTE |
Formatted contents note |
3. Tolerating slow writes in PCM -- 3.1 Introduction -- 3.2 Problem: contention from slow writes -- 3.3 Write cancellation for PCM -- 3.4 Threshold-based write cancellation -- 3.5 Adaptive write cancellation -- 3.6 Overheads: extraneous writes -- 3.7 Pausing in iterative-write devices -- 3.8 Write pausing -- 3.9 Combining write pausing and cancellation -- 3.10 Impact of write queue size -- 3.11 Concluding remarks -- |
505 8# - FORMATTED CONTENTS NOTE |
Formatted contents note |
4. Wear leveling for durability -- 4.1 Introduction -- 4.2 Figure of merit for effective wear leveling -- 4.3 Start-gap wear leveling -- 4.3.1 Design -- 4.3.2 Mapping of addresses -- 4.3.3 Overheads -- 4.3.4 Results for start-gap -- 4.3.5 A shortcoming of start-gap -- 4.4 Randomized start-gap -- 4.4.1 Feistel network based randomization -- 4.4.2 Random invertible binary matrix -- 4.4.3 Results of randomized start-gap -- 4.5 Concluding remarks -- |
505 8# - FORMATTED CONTENTS NOTE |
Formatted contents note |
5. Wear leveling under adversarial settings -- 5.1 Introduction -- 5.2 A simple attack kernel -- 5.3 Summary of secure wear leveling algorithms -- 5.4 Formulating secure wear leveling as buckets-and-balls problem -- 5.5 Write overhead of secure wear leveling -- 5.6 Adaptive wear leveling -- 5.6.1 Architecture -- 5.6.2 Attack density -- 5.6.3 Attack density for typical applications -- 5.7 Online attack detection -- 5.8 Anatomy of an attack -- 5.9 Practical attack detection -- 5.10 Implementing adaptive wear leveling -- 5.10.1 Adaptive start gap -- 5.10.2 Adaptive security refresh (SR-1) -- 5.10.3 Adaptive security refresh (SR-M) -- 5.11 Concluding remarks -- |
505 8# - FORMATTED CONTENTS NOTE |
Formatted contents note |
6. Error resilience in phase change memories -- 6.1 Introduction -- 6.2 Fault model assumptions -- 6.3 Dynamically replicated memory -- 6.3.1 Structure -- 6.3.2 Page compatibility -- 6.3.3 Error detection -- 6.3.4 Low overhead approximate pairing -- 6.4 Error correcting pointers -- 6.5 Alternate data retry and safer -- 6.6 Fine-grained embedded redirection -- 6.7 Concluding remarks -- |
505 8# - FORMATTED CONTENTS NOTE |
Formatted contents note |
7. Storage and system design with emerging non-volatile memories -- 7.1 Introduction and chapter overview -- 7.2 Storage-class memory, a system level abstraction for phase change memory -- 7.3 Storage system design -- 7.3.1 Overview of solid-state disks -- 7.3.2 The flash translation layer (FTL) -- 7.4 FTL and SSD design optimizations with storage-class memory -- 7.4.1 Addressing the small-write problem of flash SSDs -- 7.4.2 New SSD interfaces -- 7.4.3 Case study: the onyx PCM-based SSD -- 7.4.4 Discussion -- 7.5 Implications of memory system non-volatility on system design -- 7.5.1 File system design -- 7.5.2 The software interface to SCM -- 7.5.3 Non-volatility as a design knob -- 7.5.4 Discussion -- |
505 8# - FORMATTED CONTENTS NOTE |
Formatted contents note |
Bibliography -- Authors' biographies. |
506 1# - RESTRICTIONS ON ACCESS NOTE |
Terms governing access |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
510 0# - CITATION/REFERENCES NOTE |
Name of source |
Compendex |
510 0# - CITATION/REFERENCES NOTE |
Name of source |
INSPEC |
510 0# - CITATION/REFERENCES NOTE |
Name of source |
Google scholar |
510 0# - CITATION/REFERENCES NOTE |
Name of source |
Google book search |
520 3# - SUMMARY, ETC. |
Summary, etc. |
As conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems. This synthesis lecture begins by listing the requirements for a next generation memory technology and briefly surveying the landscape of novel non-volatile memories. Among these, Phase Change Memory (PCM) is emerging as a leading contender, and the authors discuss the material, device, and circuit advances underlying this exciting technology. The lecture then describes architectural solutions to enable PCM for main memories. Finally, the authors explore the impact of such byte-addressable non-volatile memories on future storage and system designs. |
530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE |
Additional physical form available note |
Also available in print. |
588 ## - SOURCE OF DESCRIPTION NOTE |
Source of description note |
Title from PDF t.p. (viewed on December 17, 2011). |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Computer storage devices. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Random access memory. |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
phase change memory |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
non-volatile memory |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
storage |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
disks |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
systems |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Gurumurthi, Sudhanva. |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Rajendran, Bipin. |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
Relationship information |
Print version: |
International Standard Book Number |
9781608456659 |
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
Uniform title |
Synthesis digital library of engineering and computer science. |
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
Uniform title |
Synthesis lectures in computer architecture ; |
Volume/sequential designation |
# 18. |
International Standard Serial Number |
1935-3243 |
856 42 - ELECTRONIC LOCATION AND ACCESS |
Materials specified |
Abstract with links to resource |
Uniform Resource Identifier |
http://ieeexplore.ieee.org/servlet/opac?bknumber=6813358 |