000 -LEADER |
fixed length control field |
05417nam a2200733 i 4500 |
001 - CONTROL NUMBER |
control field |
6812718 |
003 - CONTROL NUMBER IDENTIFIER |
control field |
IEEE |
005 - DATE AND TIME OF LATEST TRANSACTION |
control field |
20200413152902.0 |
006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS |
fixed length control field |
m eo d |
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
fixed length control field |
cr cn |||m|||a |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
110618s2011 caua foab 000 0 eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9781598297546 (electronic bk.) |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
Canceled/invalid ISBN |
9781598297539 (pbk.) |
024 7# - OTHER STANDARD IDENTIFIER |
Standard number or code |
10.2200/S00365ED1V01Y201105CAC017 |
Source of number or code |
doi |
035 ## - SYSTEM CONTROL NUMBER |
System control number |
(CaBNVSL)gtp00548368 |
035 ## - SYSTEM CONTROL NUMBER |
System control number |
(OCoLC)742535645 |
040 ## - CATALOGING SOURCE |
Original cataloging agency |
CaBNVSL |
Transcribing agency |
CaBNVSL |
Modifying agency |
CaBNVSL |
050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
Classification number |
TK7895.M4 |
Item number |
B255 2011 |
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
621.39732 |
Edition number |
22 |
100 1# - MAIN ENTRY--PERSONAL NAME |
Personal name |
Balasubramonian, Rajeev. |
245 10 - TITLE STATEMENT |
Title |
Multi-core cache hierarchies |
Medium |
[electronic resource] / |
Statement of responsibility, etc. |
Rajeev Balasubramonian, Norman Jouppi, Naveen Muralimanohar. |
260 ## - PUBLICATION, DISTRIBUTION, ETC. |
Place of publication, distribution, etc. |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : |
Name of publisher, distributor, etc. |
Morgan & Claypool, |
Date of publication, distribution, etc. |
c2011. |
300 ## - PHYSICAL DESCRIPTION |
Extent |
1 electronic text (xiv, 137 p.) : |
Other physical details |
ill., digital file. |
490 1# - SERIES STATEMENT |
Series statement |
Synthesis lectures on computer architecture, |
International Standard Serial Number |
1935-3243 ; |
Volume/sequential designation |
# 17 |
538 ## - SYSTEM DETAILS NOTE |
System details note |
Mode of access: World Wide Web. |
538 ## - SYSTEM DETAILS NOTE |
System details note |
System requirements: Adobe Acrobat Reader. |
500 ## - GENERAL NOTE |
General note |
Part of: Synthesis digital library of engineering and computer science. |
500 ## - GENERAL NOTE |
General note |
Series from website. |
504 ## - BIBLIOGRAPHY, ETC. NOTE |
Bibliography, etc. note |
Includes bibliographical references (p. 119-136). |
505 0# - FORMATTED CONTENTS NOTE |
Formatted contents note |
Preface -- Acknowledgments -- |
505 8# - FORMATTED CONTENTS NOTE |
Formatted contents note |
1. Basic elements of large cache design -- Shared vs. private caches -- Shared LLC -- Private LLC -- Workload analysis -- Centralized vs. distributed shared caches -- Non-uniform cache access -- Inclusion -- |
505 8# - FORMATTED CONTENTS NOTE |
Formatted contents note |
2. Organizing data in CMP last level caches -- Data management for a large shared NUCA cache -- Placement/migration/search policies for D-NUCA -- Replication policies in shared caches -- OS-based page placement -- Data management for a collection of private caches -- Discussion -- |
505 8# - FORMATTED CONTENTS NOTE |
Formatted contents note |
3. Policies impacting cache hit rates -- Cache partitioning for throughput and quality-of-service -- Introduction -- Throughput -- QoS policies -- Selecting a highly useful population for a large shared cache -- Replacement/insertion policies -- Novel organizations for associativity -- Block-level optimizations -- Summary -- |
505 8# - FORMATTED CONTENTS NOTE |
Formatted contents note |
4. Interconnection networks within large caches -- Basic large cache design -- Cache array design -- Cache interconnects -- Packet-switched routed networks -- The impact of interconnect design on NUCA and UCA caches -- NUCA caches -- UCA caches -- Innovative network architectures for large caches -- |
505 8# - FORMATTED CONTENTS NOTE |
Formatted contents note |
5. Technology -- Static-RAM limitations -- Parameter variation -- Modeling methodology -- Mitigating the effects of process variation -- Tolerating hard and soft errors -- Leveraging 3D stacking to resolve SRAM problems -- Emerging technologies -- 3T1D RAM -- Embedded DRAM -- Non-volatile memories -- |
505 8# - FORMATTED CONTENTS NOTE |
Formatted contents note |
6. Concluding remarks -- Bibliography -- Authors' biographies. |
506 1# - RESTRICTIONS ON ACCESS NOTE |
Terms governing access |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
510 0# - CITATION/REFERENCES NOTE |
Name of source |
Compendex |
510 0# - CITATION/REFERENCES NOTE |
Name of source |
INSPEC |
510 0# - CITATION/REFERENCES NOTE |
Name of source |
Google scholar |
510 0# - CITATION/REFERENCES NOTE |
Name of source |
Google book search |
520 3# - SUMMARY, ETC. |
Summary, etc. |
A key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energy than on-chip accesses. In addition, multi-core processors are expected to place ever higher bandwidth demands on the memory system. All these issues make it important to avoid off-chip memory access by improving the efficiency of the on-chip cache. Future multi-core processors will have many large cache banks connected by a network and shared by many cores. Hence, many important problems must be solved: cache resources must be allocated across many cores, data must be placed in cache banks that are near the accessing core, and the most important data must be identified for retention. Finally, difficulties in scaling existing technologies require adapting to and exploiting new technology constraints. The book attempts a synthesis of recent cache research that has focused on innovations for multi-core processors. It is an excellent starting point for early-stage graduate students, researchers, practitioners who wish to understand the landscape of recent cache research. The book is suitable as a reference for advanced computer architecture classes as well as for experienced researchers and VLSI engineers. |
530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE |
Additional physical form available note |
Also available in print. |
588 ## - SOURCE OF DESCRIPTION NOTE |
Source of description note |
Title from PDF t.p. (viewed on June 18, 2011). |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Cache memory. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Computer architecture. |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
Computer architecture |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
Multi-core processors |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
Cache hierarchies |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
Shared and private caches |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
Non-uniform cache access (NUCA) |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
Quality-of-service |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
Cache partitions |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
Replacement policies |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
Memory prefetch |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
On-chip networks |
653 ## - INDEX TERM--UNCONTROLLED |
Uncontrolled term |
Memory cells |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Jouppi, Norman P. |
Fuller form of name |
(Norman Paul) |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Muralimanohar, Naveen. |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
Relationship information |
Print version: |
International Standard Book Number |
9781598297539 |
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
Uniform title |
Synthesis digital library of engineering and computer science. |
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
Uniform title |
Synthesis lectures on computer architecture, |
International Standard Serial Number |
1935-3243 ; |
Volume/sequential designation |
# 17. |
856 42 - ELECTRONIC LOCATION AND ACCESS |
Materials specified |
Abstract with links to resource |
Uniform Resource Identifier |
http://ieeexplore.ieee.org/servlet/opac?bknumber=6812718 |