| 000 -LEADER |
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08492nam a2200721 i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
6813517 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20200413152901.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS |
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m eo d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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cr cn |||m|||a |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
110520s2011 caua foab 000 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9781608455652 (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| Canceled/invalid ISBN |
9781608455645 (pbk.) |
| 024 7# - OTHER STANDARD IDENTIFIER |
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| Standard number or code |
10.2200/S00346ED1V01Y201104CAC016 |
| Source of number or code |
doi |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(CaBNVSL)gtp00547876 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(OCoLC)726930429 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
CaBNVSL |
| Transcribing agency |
CaBNVSL |
| Modifying agency |
CaBNVSL |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
QA76.9.M45 |
| Item number |
S676 2011eb |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
005.43 |
| Edition number |
22 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Sorin, Daniel J. |
| 245 12 - TITLE STATEMENT |
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| Title |
A primer on memory consistency and cache coherence |
| Medium |
[electronic resource] / |
| Statement of responsibility, etc. |
Daniel J. Sorin, Mark D. Hill, David A. Wood. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : |
| Name of publisher, distributor, etc. |
Morgan & Claypool, |
| Date of publication, distribution, etc. |
c2011. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
1 electronic text (xiii, 197 p.) : |
| Other physical details |
ill., digital file. |
| 490 1# - SERIES STATEMENT |
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| Series statement |
Synthesis lectures on computer architecture, |
| International Standard Serial Number |
1935-3243 ; |
| Volume/sequential designation |
# 16 |
| 538 ## - SYSTEM DETAILS NOTE |
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| System details note |
Mode of access: World Wide Web. |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
System requirements: Adobe Acrobat Reader. |
| 500 ## - GENERAL NOTE |
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| General note |
Part of: Synthesis digital library of engineering and computer science. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Series from website. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
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| Bibliography, etc. note |
Includes bibliographical references. |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Preface -- 1. Introduction to consistency and coherence -- Consistency (a.k.a., memory consistency, memory consistency model or memory model) -- Coherence (a.k.a., cache coherence) -- A consistency and coherence quiz -- What this primer does not do -- |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
2. Coherence basics -- Baseline system model -- The problem: how incoherence could possibly occur -- Defining coherence -- Maintaining the coherence invariants -- The granularity of coherence -- The scope of coherence -- References -- |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
3. Memory consistency motivation and sequential consistency -- Problems with shared memory behavior -- What is a memory consistency model -- Consistency vs. coherence -- Basic idea of sequential consistency (SC) -- A little SC formalism -- Naive SC implementations -- A basic SC implementation with cache coherence -- Optimized SC implementations with cache coherence -- Atomic operations with SC -- Putting it all together: MIPS R10000 -- Further reading regarding SC -- References -- |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
4. Total store order and the x86 memory model -- Motivation for TSO/x86 -- Basic idea of TSO/x86 -- A little TSO formalism and an x86 conjecture -- Implementing TSO/x86 -- Atomic instructions and fences with TSO -- Atomic instructions -- Fences -- Further reading regarding TSO -- Comparing SC and TSO -- References -- |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
5. Relaxed memory consistency -- Motivation -- Opportunities to reorder memory operations -- Opportunities to exploit reordering -- An example relaxed consistency model (XC) -- The basic idea of the XC model -- Examples using fences under XC -- Formalizing XC -- Examples showing XC operating correctly -- Implementing XC -- Atomic instructions with XC -- Fences with XC -- A caveat -- Sequential consistency for data-race-free programs -- Some relaxed model concepts -- Release consistency -- Causality and write atomicity -- A relaxed memory model case study: IBM power -- Further reading and commercial relaxed memory models -- Academic literature -- Commercial models -- Comparing memory models -- How do relaxed memory models relate to each other and TSO and SC -- How good are relaxed models -- High-level language models -- References -- |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
6. Coherence protocols -- The big picture -- Specifying coherence protocols -- Example of a simple coherence protocol -- Overview of coherence protocol design space -- States -- Transactions -- Major protocol design options -- References -- |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
7. Snooping coherence protocols -- Introduction to snooping -- Baseline snooping protocol -- High-level protocol specification -- Simple snooping system model: atomic requests -- Atomic transactions -- Baseline snooping system model: non-atomic requests, atomic transactions -- Running example -- Protocol simplifications -- Adding the exclusive state -- Motivation -- Getting to the exclusive state -- High-level specification of protocol -- Detailed specification -- Running example -- Adding the owned state -- Motivation -- High-level protocol specification -- Detailed protocol specification -- Running example -- Non-atomic bus -- Motivation -- In-order vs. out-of-order responses -- Non-atomic system model -- An MSI protocol with a split-transaction bus -- An optimized, non-stalling MSI protocol with a split-transaction bus -- Optimizations to the bus interconnection network -- Separate non-bus network for data responses -- Logical bus for coherence requests -- Case studies -- Sun Starfire E10000 -- IBM Power5 -- Discussion and the future of snooping -- References -- |
| 505 8# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
8. Directory coherence protocols -- Introduction to directory protocols -- Baseline directory system -- Directory system model -- High-level protocol specification -- Avoiding deadlock -- Detailed protocol specification -- Protocol operation -- Protocol simplifications -- Adding the exclusive state -- High-level protocol specification -- Detailed protocol specification -- Adding the owned state -- High-level protocol specification -- Detailed protocol specification -- Representing directory state -- Coarse directory -- Limited pointer directory -- Directory organization -- Directory cache backed by DRAM -- Inclusive directory caches -- Null directory cache (with no backing store) -- Performance and scalability optimizations -- Distributed directories -- Non-stalling directory protocols -- Interconnection networks without point-to-point ordering -- Silent vs. non-silent evictions of blocks in state S -- Case studies -- SGI origin 2000 -- Coherent hypertransport -- Hypertransport assist -- Intel QPI -- Discussion and the future of directory protocols -- References -- |
| 505 8# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
9. Advanced topics in coherence -- System models -- Instruction caches -- Translation lookaside buffers (TLBS) -- Virtual caches -- Write-through caches -- Coherent direct memory access (DMA) -- Multi-level caches and hierarchical coherence protocols -- Performance optimizations -- Migratory sharing optimization -- False sharing optimizations -- Maintaining liveness -- Deadlock -- Livelock -- Starvation -- Token coherence -- The future of coherence -- References -- Author biographies. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE |
|---|
| Terms governing access |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Compendex |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
INSPEC |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google scholar |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google book search |
| 520 3# - SUMMARY, ETC. |
|---|
| Summary, etc. |
Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high level concepts as well as specific, concrete examples from real-world systems. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE |
|---|
| Additional physical form available note |
Also available in print. |
| 588 ## - SOURCE OF DESCRIPTION NOTE |
|---|
| Source of description note |
Title from PDF t.p. (viewed on May 20, 2011). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Memory management (Computer science) |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Cache memory. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Distributed shared memory. |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Computer architecture |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Memory consistency |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Cache coherence |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Shared memory |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Memory systems |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Multicore processor |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Multiprocessor |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Hill, Mark D. |
| Fuller form of name |
(Mark Donald) |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Wood, David A. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Relationship information |
Print version: |
| International Standard Book Number |
9781608455645 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis digital library of engineering and computer science. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis lectures on computer architecture, |
| International Standard Serial Number |
1935-3243 ; |
| Volume/sequential designation |
# 16. |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Abstract with links to resource |
| Uniform Resource Identifier |
http://ieeexplore.ieee.org/servlet/opac?bknumber=6813517 |
