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Digital system verification (Record no. 561741)

000 -LEADER
fixed length control field 05181nam a2200553 i 4500
001 - CONTROL NUMBER
control field 6813106
003 - CONTROL NUMBER IDENTIFIER
control field IEEE
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20200413152857.0
006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS
fixed length control field m eo d
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr cn |||m|||a
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 100306s2010 caua foab 000 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781608451791 (electronic bk.)
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
Canceled/invalid ISBN 9781608451784 (pbk.)
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.2200/S00257ED1V01Y201002DCS027
Source of number or code doi
035 ## - SYSTEM CONTROL NUMBER
System control number (CaBNVSL)gtp00538726
035 ## - SYSTEM CONTROL NUMBER
System control number (OCoLC)588869825
040 ## - CATALOGING SOURCE
Original cataloging agency CaBNVSL
Transcribing agency CaBNVSL
Modifying agency CaBNVSL
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7874.58
Item number .L53 2010
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.381548
Edition number 22
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Li, Lun,
Dates associated with a name 1970-
245 10 - TITLE STATEMENT
Title Digital system verification
Medium [electronic resource] :
Remainder of title a combined formal methods and simulation framework /
Statement of responsibility, etc. Lun Li, Mitchell A. Thornton.
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) :
Name of publisher, distributor, etc. Morgan & Claypool Publishers,
Date of publication, distribution, etc. c2010.
300 ## - PHYSICAL DESCRIPTION
Extent 1 electronic text (79 p. : ill.) :
Other physical details digital file.
490 1# - SERIES STATEMENT
Series statement Synthesis lectures on digital circuits and systems,
International Standard Serial Number 1932-3174 ;
Volume/sequential designation # 27
538 ## - SYSTEM DETAILS NOTE
System details note Mode of access: World Wide Web.
538 ## - SYSTEM DETAILS NOTE
System details note System requirements: Adobe Acrobat reader.
500 ## - GENERAL NOTE
General note Part of: Synthesis digital library of engineering and computer science.
500 ## - GENERAL NOTE
General note Series from website.
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc. note Includes bibliographical references (p. 71-78).
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note 1. Introduction -- 2. Formal methods background -- Existing techniques for verification -- Equivalence checking -- Model checking -- Bounded model checking -- Fundamental data structures and algorithms -- Boolean functions and finite state machines -- Image computation using the transition relation -- Symbolic FSM state space traversal -- Binary decision diagrams -- The Boolean satisfiability problem -- Image computation -- BDD-based approach -- SAT based methods -- Hybrid approaches -- A genetic algorithm approach for the BDD-based method -- Combing BDD and SAT in one framework -- Summary --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 3. Simulation approaches -- Compiled simulation and event-driven simulation -- Compiled simulation -- Event-driven simulation -- Timing model -- Signal modeling -- Abstraction level -- Fault simulation -- Logic simulators -- Current needs in simulation --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 4. Integrated design validation system -- System description -- Complexity analyzer -- Design partitioning -- Coverage analysis -- Verification and simulation tools comprising IDV -- Symbolic trajectory evaluation -- Validation flow with IDV -- IDV implementation architecture --
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 5. Conclusion and summary -- Bibliography -- Authors' biographies.
506 1# - RESTRICTIONS ON ACCESS NOTE
Terms governing access Abstract freely available; full-text restricted to subscribers or individual document purchasers.
510 0# - CITATION/REFERENCES NOTE
Name of source Compendex
510 0# - CITATION/REFERENCES NOTE
Name of source INSPEC
510 0# - CITATION/REFERENCES NOTE
Name of source Google scholar
510 0# - CITATION/REFERENCES NOTE
Name of source Google book search
520 3# - SUMMARY, ETC.
Summary, etc. Integrated circuit capacity follows Moore's law, and chips are commonly produced at the time of this writing with over 70 million gates per device. Ensuring correct functional behavior of such large designs before fabrication poses an extremely challenging problem. Formal verification validates the correctness of the implementation of a design with respect to its specification through mathematical proof techniques. Formal techniques have been emerging as commercialized EDA tools in the past decade. Simulation remains a predominantly used tool to validate a design in industry. After more than 50 years of development, simulation methods have reached a degree of maturity, however, new advances continue to be developed in the area. A simulation approach for functional verification can theoretically validate all possible behaviors of a design but requires excessive computational resources. Rapidly evolving markets demand short design cycles while the increasing complexity of a design causes simulation approaches to provide less and less coverage. Formal verification is an attractive alternative since 100% coverage can be achieved; however, large designs impose unrealistic computational requirements. Combining formal verification and simulation into a single integrated circuit validation framework is an attractive alternative. This book focuses on an Integrated Design Validation (IDV) system that provides a framework for design validation and takes advantage of current technology in the areas of simulation and formal verification resulting in a practical validation engine with reasonable runtime. After surveying the basic principles of formal verification and simulation, this book describes the IDV approach to integrated circuit functional validation.
530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE
Additional physical form available note Also available in print.
588 ## - SOURCE OF DESCRIPTION NOTE
Source of description note Title from PDF t.p. (viewed on March 6, 2010).
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Integrated circuits
General subdivision Verification.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Formal methods (Computer science)
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Integrated circuits
General subdivision Computer simulation.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Thornton, Mitchell Aaron.
730 0# - ADDED ENTRY--UNIFORM TITLE
Uniform title Synthesis digital library of engineering and computer science.
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Synthesis lectures on digital circuits and systems,
International Standard Serial Number 1932-3174 ;
Volume/sequential designation # 27.
856 42 - ELECTRONIC LOCATION AND ACCESS
Materials specified Abstract with links to resource
Uniform Resource Identifier http://ieeexplore.ieee.org/servlet/opac?bknumber=6813106
Holdings
Withdrawn status Lost status Damaged status Not for loan Permanent Location Current Location Date acquired Barcode Date last seen Price effective from Koha item type
        PK Kelkar Library, IIT Kanpur PK Kelkar Library, IIT Kanpur 2020-04-13 EBKE241 2020-04-13 2020-04-13 E books

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