| 000 -LEADER |
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| fixed length control field |
09062nam a2200601 i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
6812772 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20200413152853.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS |
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m eo d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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cr cn |||m|||a |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
090309s2009 caua foab 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9781598296907 (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781598296891 (pbk.) |
| 024 7# - OTHER STANDARD IDENTIFIER |
|---|
| Standard number or code |
10.2200/S00160ED1V01Y200811DCS018 |
| Source of number or code |
doi |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(CaBNVSL)gtp00533527 |
| 035 ## - SYSTEM CONTROL NUMBER |
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| System control number |
(OCoLC)316237913 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
CaBNVSL |
| Transcribing agency |
CaBNVSL |
| Modifying agency |
CaBNVSL |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7868.A79 |
| Item number |
T553 2009 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.3815 |
| Edition number |
22 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Tinder, Richard F., |
| Dates associated with a name |
1930- |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Asynchronous sequential machine design and analysis |
| Medium |
[electronic resource] : |
| Remainder of title |
a comprehensive development of the design and analysis of clock-independent state machines and systems / |
| Statement of responsibility, etc. |
Richard F. Tinder. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : |
| Name of publisher, distributor, etc. |
Morgan & Claypool Publishers, |
| Date of publication, distribution, etc. |
c2009. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
1 electronic text (xv, 235 p. : ill.) : |
| Other physical details |
digital file. |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
Synthesis lectures on digital circuits and systems, |
| International Standard Serial Number |
1932-3174 ; |
| Volume/sequential designation |
# 18 |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
Mode of access: World Wide Web. |
| 538 ## - SYSTEM DETAILS NOTE |
|---|
| System details note |
System requirements: Adobe Acrobat reader. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Part of: Synthesis digital library of engineering and computer science. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Series from website. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references (p. 201-202) and index. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Background fundaments for design and analysis of asynchronous state machines -- Introduction and background -- Features of and need for asynchronous finite state machines -- Fundamental mode of operation and lumped path delay models -- Stability criteria and the excitation table for LPD models -- Nested set-reset element models for asynchronous sequential machines -- Fully documented state diagram, sum rule and mutually exclusive requirement -- The mapping algorithm -- Application of the mapping algorithm to simple LPD model designs -- Mixed-logic notation and the cardinal rule -- Design of basic memory elements and their characteristics -- Basic SR cells -- Muller C-elements -- Summary of the excitation tables -- Huffman vs. Muller asynchronous FSMs -- Simple FSM design and initialization -- The extended Y-SR mapping algorithm -- Application to FSM design with C-elements -- Initialization of asynchronous FSMs -- Sanity circuits, design and applications -- Detection and elimination of timing defects in asynchronous FSMs -- Endless cycles -- Races and critical races -- Static hazards in the NS and output forming logic -- Detection and elimination of static hazards in the NS forming logic -- Detection and elimination of static hazards in the output forming logic -- Dynamic hazards and function hazards -- Output race glitches, detection and elimination -- Essential hazards, detection and elimination -- Minimum requirements for E-hazard and D-trio formation -- A simple example -- Metastable conditions in C-elements -- Design of single transition time machines -- The array algebraic approach -- Design example using C-elements -- Essential hazard analysis in STT FSMs -- Computer aided STT FSM design -- Summary of hazard effects and their elimination in STT FSM designs -- Design of one-hot asynchronous FSMs -- Introduction to the one-hot approach -- Characteristics of the one-hot method -- Design example using C-elements -- Essential hazards in one-hot asynchronous FSMs -- Design of pulse mode FSMs -- Models and characteristics of the pulse mode -- Requirements and characteristics of the pulse mode approach -- Toggle modules as the memory elements -- A design example -- Other memory elements suitable for pulse mode design -- Debouncing circuits -- Analysis of asynchronous FSMs -- Procedure for analyzing any asynchronous FSM -- Example of an LPD model FSM analysis -- E-hazard and D-trio analyses of the PGM -- Example of an STT FSM analysis -- Example of a one-hot FSM analysis -- Example of a pulse mode FSM analysis -- Self-timed systems, programmable sequencers, and arbiters -- Externally asynchronous/internally clocked systems -- Basic architecture and system characteristics -- DFLOP memory element design with C-elements -- D-trio analysis of the resolver FSM -- Simple example of an EAIC FSM design -- The metastable detection stage -- Frequency characteristics and NS logic constraints of EAIC systems -- Parallel/serial processing with cascaded EAIC microcontrollers -- Characteristics -- Summary of the salient features of EAIC systems -- Cascadable asynchronous programmable sequencers (CAPS) and time-shared system design -- Microprogrammable asynchronous controller modules -- MAC module characteristics for use with CAPS system architecture -- C-element design of a 2 x 2 MAC module -- Stepwise operation of the MAC module -- Cascading the MAC modules -- Programming the MAC module, four examples -- Time-shared FSM operation by using cascaded MAC modules -- Asynchronous one-hot programmable sequencer systems -- General architecture -- Design of one-hot sequencers -- Time-shared multiple FSM operation by a single A-OPS -- A-OPS software capabilities used in this text -- Arbiter modules -- Bus arbiter module -- Multiple input bus arbiters -- Priority stand-alone arbiters -- Handshake arbiters with acknowledgment (done) signals -- Rotating token arbiters -- Applications -- Appendix A -- Brief reviews -- A.1 Mixed-logic gate symbology and conjugate gate forms -- A.2 And/or laws and the EQV/XOR laws of Boolean algebra (dual relations) -- A.3 Entered variable K-map compression and minimization -- A.3.1 Incompletely specified functions -- Appendix B End-of-chapter problems -- Endnotes -- General background directly supporting material in this text -- Alternative approaches to asynchronous state machine design and analysis -- Important historical contributions to asynchronous circuit synthesis -- Sources related to the subject of EAIC systems discussed in this text -- Glossary of terms, expressions, and abbreviations -- Author biography -- Index. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE |
|---|
| Terms governing access |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Compendex |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
INSPEC |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google scholar |
| 510 0# - CITATION/REFERENCES NOTE |
|---|
| Name of source |
Google book search |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
Asynchronous Sequential Machine Design and Analysis provides a lucid, in-depth treatment of asynchronous state machine design and analysis presented in two parts: Part I on the background fundamentals related to asynchronous sequential logic circuits generally, and Part II on self-timed systems, high-performance asynchronous programmable sequencers, and arbiters. Part I provides a detailed review of the background fundamentals for the design and analysis of asynchronous finite state machines (FSMs). Included are the basic models, use of fully documented state diagrams, and the design and characteristics of basic memory cells and Muller C-elements. Simple FSMs using C-elements illustrate the design process. The detection and elimination of timing defects in asynchronous FSMs are covered in detail. This is followed by the array algebraic approach to the design of single-transition-time machines and use of CAD software for that purpose, one-hot asynchronous FSMs, and pulse mode FSMs. Part I concludes with the analysis procedures for asynchronous state machines. Part II is concerned mainly with self-timed systems, programmable sequencers, and arbiters. It begins with a detailed treatment of externally asynchronous/internally clocked (or pausable) systems that are delay-insensitive and metastability-hardened. This is followed by defect-free cascadable asynchronous sequencers, and defect-free one-hot asynchronous programmable sequencers--their characteristics, design, and applications. Part II concludes with arbiter modules of various types, those with and without metastability protection, together with applications. Presented in the appendices are brief reviews covering mixed-logic gate symbology, Boolean algebra, and entered-variable K-map minimization. End-of-chapter problems and a glossary of terms, expressions, and abbreviations contribute to the reader's learning experience. Five productivity tools are made available specifically for use with this text and briefly discussed in this front matter. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE |
|---|
| Additional physical form available note |
Also available in print. |
| 588 ## - SOURCE OF DESCRIPTION NOTE |
|---|
| Source of description note |
Title from PDF t.p. (viewed on March 9, 2009). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Asynchronous circuits |
| General subdivision |
Mathematical models. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Sequential circuits |
| General subdivision |
Mathematical models. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Sequential machine theory |
| General subdivision |
Mathematical models. |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Asynchronous |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Sequential |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Sequencers |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Logic |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Machines |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Digital |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Self-timed |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) |
|---|
| Topical term or geographic name as entry element |
Arbiters |
| 730 0# - ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis digital library of engineering and computer science. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Synthesis lectures on digital circuits and systems ; |
| Volume/sequential designation |
# 18. |
| 856 42 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Materials specified |
Abstract with links to resource |
| Uniform Resource Identifier |
http://ieeexplore.ieee.org/servlet/opac?bknumber=6812772 |
