Programming for hybrid multi/manycore MPP systems (Record no. 558391)
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000 -LEADER | |
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fixed length control field | 02707 a2200229 4500 |
005 - DATE AND TIME OF LATEST TRANSACTION | |
control field | 20180122123956.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 180122b xxu||||| |||| 00| 0 eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
ISBN | 9781439873717 |
040 ## - CATALOGING SOURCE | |
Transcribing agency | IIT Kanpur |
041 ## - LANGUAGE CODE | |
Language code of text/sound track or separate title | eng |
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
Classification number | 004.22 |
Item number | L577p |
100 ## - MAIN ENTRY--AUTHOR NAME | |
Personal name | Levesque, John |
245 ## - TITLE STATEMENT | |
Title | Programming for hybrid multi/manycore MPP systems |
Statement of responsibility, etc | John Levesque and Aaron Vose |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
Name of publisher | CRC Press |
Year of publication | 2018 |
Place of publication | Boca Raton |
300 ## - PHYSICAL DESCRIPTION | |
Number of Pages | xxxv, 305p |
440 ## - SERIES STATEMENT/ADDED ENTRY--TITLE | |
Title | Chapman & Hall/CRC computational science series |
490 ## - SERIES STATEMENT | |
Series statement | / edited by Horst Simon |
520 ## - SUMMARY, ETC. | |
Summary, etc | "Ask not what your compiler can do for you, ask what you can do for your compiler." --John Levesque, Director of Cray’s Supercomputing Centers of Excellence The next decade of computationally intense computing lies with more powerful multi/manycore nodes where processors share a large memory space. These nodes will be the building block for systems that range from a single node workstation up to systems approaching the exaflop regime. The node itself will consist of 10’s to 100’s of MIMD (multiple instruction, multiple data) processing units with SIMD (single instruction, multiple data) parallel instructions. Since a standard, affordable memory architecture will not be able to supply the bandwidth required by these cores, new memory organizations will be introduced. These new node architectures will represent a significant challenge to application developers. Programming for Hybrid Multi/Manycore MPP Systems attempts to briefly describe the current state-of-the-art in programming these systems, and proposes an approach for developing a performance-portable application that can effectively utilize all of these systems from a single application. The book starts with a strategy for optimizing an application for multi/manycore architectures. It then looks at the three typical architectures, covering their advantages and disadvantages. The next section of the book explores the other important component of the target―the compiler. The compiler will ultimately convert the input language to executable code on the target, and the book explores how to make the compiler do what we want. The book then talks about gathering runtime statistics from running the application on the important problem sets previously discussed. How best to utilize available memory bandwidth and virtualization is covered next, along with hybridization of a program. The last part of the book includes several major applications, and examines future hardware advancements and how the application developer may prepare for those advancements. |
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical Term | Computer architecture |
700 ## - ADDED ENTRY--PERSONAL NAME | |
Personal name | Vose, Aaron |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Koha item type | Books |
Withdrawn status | Lost status | Damaged status | Not for loan | Collection code | Permanent Location | Current Location | Date acquired | Source of acquisition | Cost, normal purchase price | Full call number | Accession Number | Cost, replacement price | Koha item type |
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General Stacks | PK Kelkar Library, IIT Kanpur | PK Kelkar Library, IIT Kanpur | 2018-01-16 | 1 | 4823.71 | 004.22 L577p | A183430 | 6029.64 | Books |