000 -LEADER |
fixed length control field |
03616nam a22005055i 4500 |
001 - CONTROL NUMBER |
control field |
978-1-4020-6195-0 |
003 - CONTROL NUMBER IDENTIFIER |
control field |
DE-He213 |
005 - DATE AND TIME OF LATEST TRANSACTION |
control field |
20161121231154.0 |
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
fixed length control field |
cr nn 008mamaa |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
100301s2007 ne | s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9781402061950 |
-- |
978-1-4020-6195-0 |
024 7# - OTHER STANDARD IDENTIFIER |
Standard number or code |
10.1007/978-1-4020-6195-0 |
Source of number or code |
doi |
050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
Classification number |
TK7888.4 |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
TJFC |
Source |
bicssc |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
TEC008010 |
Source |
bisacsh |
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
621.3815 |
Edition number |
23 |
100 1# - MAIN ENTRY--PERSONAL NAME |
Personal name |
Ho, Tsung-Yi. |
Relator term |
author. |
245 10 - TITLE STATEMENT |
Title |
Full-Chip Nanometer Routing Techniques |
Medium |
[electronic resource] / |
Statement of responsibility, etc. |
by Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen. |
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE |
Place of production, publication, distribution, manufacture |
Dordrecht : |
Name of producer, publisher, distributor, manufacturer |
Springer Netherlands, |
Date of production, publication, distribution, manufacture, or copyright notice |
2007. |
300 ## - PHYSICAL DESCRIPTION |
Extent |
XVIII, 102 p. |
Other physical details |
online resource. |
336 ## - CONTENT TYPE |
Content type term |
text |
Content type code |
txt |
Source |
rdacontent |
337 ## - MEDIA TYPE |
Media type term |
computer |
Media type code |
c |
Source |
rdamedia |
338 ## - CARRIER TYPE |
Carrier type term |
online resource |
Carrier type code |
cr |
Source |
rdacarrier |
347 ## - DIGITAL FILE CHARACTERISTICS |
File type |
text file |
Encoding format |
PDF |
Source |
rda |
490 1# - SERIES STATEMENT |
Series statement |
Analog Circuits And Signal Processing Series |
505 0# - FORMATTED CONTENTS NOTE |
Formatted contents note |
Routing Challenges for Nanometer Technology -- Multilevel Full-Chip Routing Considering Crosstalk And Performance -- Multilevel Full-Chip Routing Considering Antenna Effect Avoidance -- Multilevel Full-Chip Routing For The X-Based Architecture -- Concluding Remarks And Future Work. |
520 ## - SUMMARY, ETC. |
Summary, etc. |
As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of physics-aware and manufacturing-aware routing. At 90 nm and below, there are so many signal-integrity issues that design teams cannot manually correct them all. At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Engineering. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Computer-aided engineering. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Electronic circuits. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Nanotechnology. |
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Engineering. |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Circuits and Systems. |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Computer-Aided Engineering (CAD, CAE) and Design. |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name entry element |
Nanotechnology. |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Chang, Yao-Wen. |
Relator term |
author. |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Chen, Sao-Jie. |
Relator term |
author. |
710 2# - ADDED ENTRY--CORPORATE NAME |
Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
773 0# - HOST ITEM ENTRY |
Title |
Springer eBooks |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
Relationship information |
Printed edition: |
International Standard Book Number |
9781402061943 |
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
Uniform title |
Analog Circuits And Signal Processing Series |
856 40 - ELECTRONIC LOCATION AND ACCESS |
Uniform Resource Identifier |
http://dx.doi.org/10.1007/978-1-4020-6195-0 |
912 ## - |
-- |
ZDB-2-ENG |