| 000 -LEADER |
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| fixed length control field |
04192nam a22005535i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
978-0-387-25556-9 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20161121231107.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
100301s2006 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9780387255569 |
| -- |
978-0-387-25556-9 |
| 024 7# - OTHER STANDARD IDENTIFIER |
|---|
| Standard number or code |
10.1007/b135575 |
| Source of number or code |
doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
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| Classification number |
TK7888.4 |
| 072 #7 - SUBJECT CATEGORY CODE |
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| Subject category code |
TJFC |
| Source |
bicssc |
| 072 #7 - SUBJECT CATEGORY CODE |
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| Subject category code |
TEC008010 |
| Source |
bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.3815 |
| Edition number |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Bergeron, Janick. |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Verification Methodology Manual for SystemVerilog |
| Medium |
[electronic resource] / |
| Statement of responsibility, etc. |
by Janick Bergeron, Eduard Cerny, Alan Hunter, Andrew Nightingale. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE |
|---|
| Place of production, publication, distribution, manufacture |
Boston, MA : |
| Name of producer, publisher, distributor, manufacturer |
Springer US, |
| Date of production, publication, distribution, manufacture, or copyright notice |
2006. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
XVII, 503 p. |
| Other physical details |
online resource. |
| 336 ## - CONTENT TYPE |
|---|
| Content type term |
text |
| Content type code |
txt |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
|---|
| Media type term |
computer |
| Media type code |
c |
| Source |
rdamedia |
| 338 ## - CARRIER TYPE |
|---|
| Carrier type term |
online resource |
| Carrier type code |
cr |
| Source |
rdacarrier |
| 347 ## - DIGITAL FILE CHARACTERISTICS |
|---|
| File type |
text file |
| Encoding format |
PDF |
| Source |
rda |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Verification Planning -- Assertions -- Testbench Infrastructure -- Stimulus and Response -- Coverage-Driven Verification -- Assertions for Formal Tools -- System-Level Verification -- Processor Integration Verification. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
Functional verification remains one of the single biggest challenges in the development of complex system-on-chip (SoC) devices. Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that these diverse new technologies have led to a proliferation of verification point tools, most with their own languages and methodologies. Fortunately, a solution is at hand. SystemVerilog is a unified language that serves both design and verification engineers by including RTL design constructs, assertions and a rich set of verification constructs. SystemVerilog is an industry standard that is well supported by a wide range of verification tools and platforms. A single language fosters the development of a unified simulation-based verification tool or platform. Consolidation of point tools into a unified platform and convergence to a unified language enable the development of a unified verification methodology that can be used on a wide range of SoC projects. ARM and Synopsys have worked together to define just such a methodology in the Verification Methodology Manual for SystemVerilog. This book is based upon best verification practices by ARM, Synopsys and their customers. Verification Methodology Manual for SystemVerilog is a blueprint for verification success, guiding SoC teams in building a reusable verification environment taking full advantage of design-for-verification techniques, constrained-random stimulus generation, coverage-driven verification, formal verification and other advanced technologies to help solve their current and future verification problems. This book is appropriate for anyone involved in the design or verification of a complex chip or anyone who would like to know more about the capabilities of SystemVerilog. Following the Verification Methodology Manual for SystemVerilog will give SoC development teams and project managers the confidence needed to tape out a complex design, secure in the knowledge that the chip will function correctly in the real world. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
Programming languages (Electronic computers). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
Computer-aided engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
Electrical engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electronics. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Microelectronics. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electronic circuits. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
Programming Languages, Compilers, Interpreters. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
Computer-Aided Engineering (CAD, CAE) and Design. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
Electronics and Microelectronics, Instrumentation. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electrical Engineering. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Cerny, Eduard. |
| Relator term |
author. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Hunter, Alan. |
| Relator term |
author. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Nightingale, Andrew. |
| Relator term |
author. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
|---|
| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
|---|
| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Relationship information |
Printed edition: |
| International Standard Book Number |
9780387255385 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
http://dx.doi.org/10.1007/b135575 |
| 912 ## - |
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| -- |
ZDB-2-ENG |
