| 000 -LEADER |
|---|
| fixed length control field |
03332nam a22005295i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
978-1-4020-8573-4 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20161121230536.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
100301s2008 ne | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781402085734 |
| -- |
978-1-4020-8573-4 |
| 024 7# - OTHER STANDARD IDENTIFIER |
|---|
| Standard number or code |
10.1007/978-1-4020-8573-4 |
| Source of number or code |
doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7800-8360 |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7874-7874.9 |
| 072 #7 - SUBJECT CATEGORY CODE |
|---|
| Subject category code |
TJF |
| Source |
bicssc |
| 072 #7 - SUBJECT CATEGORY CODE |
|---|
| Subject category code |
TEC008000 |
| Source |
bisacsh |
| 072 #7 - SUBJECT CATEGORY CODE |
|---|
| Subject category code |
TEC008070 |
| Source |
bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.381 |
| Edition number |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Stefanović, Danica. |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Structured Analog CMOS Design |
| Medium |
[electronic resource] / |
| Statement of responsibility, etc. |
by Danica Stefanović, Maher Kayal. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE |
|---|
| Place of production, publication, distribution, manufacture |
Dordrecht : |
| Name of producer, publisher, distributor, manufacturer |
Springer Netherlands, |
| Date of production, publication, distribution, manufacture, or copyright notice |
2008. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
XII, 283 p. |
| Other physical details |
online resource. |
| 336 ## - CONTENT TYPE |
|---|
| Content type term |
text |
| Content type code |
txt |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
|---|
| Media type term |
computer |
| Media type code |
c |
| Source |
rdamedia |
| 338 ## - CARRIER TYPE |
|---|
| Carrier type term |
online resource |
| Carrier type code |
cr |
| Source |
rdacarrier |
| 347 ## - DIGITAL FILE CHARACTERISTICS |
|---|
| File type |
text file |
| Encoding format |
PDF |
| Source |
rda |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
Analog Circuits and Signal Processing |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Transistor level design -- Bsim To Ekv Conversion -- Basic analog structures -- Procedural design scenarios -- PAD tool -- Topology variants -- Practical example: the design of analog amplifiers in the Delta-Sigma modulator system. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The proposed transistor-level design procedure is based on the EKV modeling approach and relies on the device inversion level as a fundamental design variable. Since all important design parameters can be expressed as continuous functions of the device inversion level, the design optimum as well as the technology limits can be easily found. The basic design concept consists in analog cell partitioning into the basic analog structures and sizing of these basic analog structures in a predefined procedural design sequence. The procedural design sequence ensures the correct propagation of design specifications, the verification of parameter limits and the local optimization loops. The proposed design procedure is also implemented as a CAD tool that follows this book. Finally, as a practical example, the design of analog amplifiers in a hybrid multi-bit Delta-Sigma modulator system is described in detail from system level to transistor level. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electronics. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Microelectronics. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electronic circuits. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electronics and Microelectronics, Instrumentation. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Processor Architectures. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Kayal, Maher. |
| Relator term |
author. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
|---|
| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
|---|
| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Relationship information |
Printed edition: |
| International Standard Book Number |
9781402085727 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Analog Circuits and Signal Processing |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
http://dx.doi.org/10.1007/978-1-4020-8573-4 |
| 912 ## - |
|---|
| -- |
ZDB-2-ENG |
