| 000 -LEADER |
|---|
| fixed length control field |
03120nam a22004335i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
978-1-4020-8446-1 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20161121230536.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
100301s2008 ne | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781402084461 |
| -- |
978-1-4020-8446-1 |
| 024 7# - OTHER STANDARD IDENTIFIER |
|---|
| Standard number or code |
10.1007/978-1-4020-8446-1 |
| Source of number or code |
doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7888.4 |
| 072 #7 - SUBJECT CATEGORY CODE |
|---|
| Subject category code |
TJFC |
| Source |
bicssc |
| 072 #7 - SUBJECT CATEGORY CODE |
|---|
| Subject category code |
TEC008010 |
| Source |
bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.3815 |
| Edition number |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Williams, John. |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Digital VLSI Design with Verilog |
| Medium |
[electronic resource] : |
| Remainder of title |
A Textbook from Silicon Valley Technical Institute / |
| Statement of responsibility, etc. |
by John Williams. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE |
|---|
| Place of production, publication, distribution, manufacture |
Dordrecht : |
| Name of producer, publisher, distributor, manufacturer |
Springer Netherlands, |
| Date of production, publication, distribution, manufacture, or copyright notice |
2008. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
XXIV, 436 p. |
| Other physical details |
online resource. |
| 336 ## - CONTENT TYPE |
|---|
| Content type term |
text |
| Content type code |
txt |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
|---|
| Media type term |
computer |
| Media type code |
c |
| Source |
rdamedia |
| 338 ## - CARRIER TYPE |
|---|
| Carrier type term |
online resource |
| Carrier type code |
cr |
| Source |
rdacarrier |
| 347 ## - DIGITAL FILE CHARACTERISTICS |
|---|
| File type |
text file |
| Encoding format |
PDF |
| Source |
rda |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Week 1 Class 1 -- Week 1 Class 2 -- Week 2 Class 1 -- Week 2 Class 2 -- Week 3 Class 1 -- Week 3 Class 2 -- Week 4 Class 1 -- Week 4 Class 2 -- Week 5 Class 1 -- Week 5 Class 2 -- Week 6 Class 1 -- Week 6 Class 2 -- Week 7 Class 1 -- Week 7 Class 2 -- Week 8 Class 1 -- Week 8 Class 2 -- Week 9 Class 1 -- Week 9 Class 2 -- Week 10 Class 1 -- Week 10 Class 2 -- Week 11 Class 1 -- Week 11 Class 2 -- Week 12 Class 1 -- Week 12 Class 2. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. For a reader with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book. A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back-annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test. Coverage of specific devices includes basic discussion and exercises on flip-flops, latches, combinational logic, muxes, counters, shift-registers, decoders, state machines, memories (including parity and ECC), FIFOs, and PLLs. Verilog specify blocks, with their path delays and timing checks, also are covered. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Programming languages (Electronic computers). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electronic circuits. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Programming Languages, Compilers, Interpreters. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
|---|
| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
|---|
| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Relationship information |
Printed edition: |
| International Standard Book Number |
9781402084454 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
http://dx.doi.org/10.1007/978-1-4020-8446-1 |
| 912 ## - |
|---|
| -- |
ZDB-2-ENG |
