| 000 -LEADER |
|---|
| fixed length control field |
00807pam a2200193a 44500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
160408b1984 xxu||||| |||| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
P K Kelkar Library, IIT Kanpur |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.38173 |
| Item number |
L829b |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
|
| 245 0# - TITLE STATEMENT |
|---|
| Title |
Logic minimization algorithms for VLSI synthesis |
| Statement of responsibility, etc. |
Robert K. Brayton ...[et al.] |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Boston |
| Name of publisher, distributor, etc. |
Kluwer Academic Publishers |
| Date of publication, distribution, etc. |
1984 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
ix, 193p |
| 440 ## - SERIES STATEMENT/ADDED ENTRY--TITLE |
|---|
| Title |
The Kluwer International Series In Engineering And Computer Science: Vlsi, Computer Architecture, And Digital Signal Processing / Edited By Jonathan Allen |
| Volume/sequential designation |
|
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Logic design |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Integrated circuits -- Very large scale integration |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Integrated circuits Design and construction -- Data processing |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Brayton, Robert K. |
| 997 ## - |
|---|
| -- |
A102483 s C |
