Welcome to P K Kelkar Library, Online Public Access Catalogue (OPAC)

HIERARCHICAL MODELING FOR VLSI CIRCUIT TESTING (Record no. 327830)

000 -LEADER
fixed length control field 00575pam a2200181a 44500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 160408bc1990 xxu||||| |||| 00| 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 079239058X
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.38173
Item number B469h
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Bhattacharya, Debashis
245 1# - TITLE STATEMENT
Title HIERARCHICAL MODELING FOR VLSI CIRCUIT TESTING
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Boston
Name of publisher, distributor, etc. Kluwer Academic Pub.
Date of publication, distribution, etc. c1990
300 ## - PHYSICAL DESCRIPTION
Extent x,159
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Very Large Scale Integration -- Testing
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Integrated Circuits -- Very Large Scale Integration -- Computer Simulation
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Hayes, John P.
964 ## -
-- CIRC
997 ## -
-- A113644 C
Holdings
Withdrawn status Lost status Damaged status Not for loan Collection code Permanent Location Current Location Date acquired Full call number Barcode Date last seen Price effective from Koha item type
        General Stacks PK Kelkar Library, IIT Kanpur PK Kelkar Library, IIT Kanpur 2007-08-12 621.38173 B469h A113644 2016-04-08 2016-04-08 Books

Powered by Koha